Electronics Design Engineer with experience in leading embedded system design for industrial instruments and prior experience in semiconductor design for CMOS & MEMS devices.
- Over 9 years of experience with Industrial Electronic Design, Analog Integrated Circuits, Embedded Systems, MEMS Technology and Digital Signal Processing
- Strong working knowledge of High Speed and Low power ASIC, CMOS and PCB design techniques including analysis of power consumption variations and microwave signal integrity analysis.
- Worked on diverse projects involving high performance and low power CMOS circuit design, layout and Tape-out
- Adept in using Altium Designer, Orcad, LabView, Cadence ICFB and SPICE
- Accomplished programmer with good command over languages such as Embedded C, C++, C#, VHDL/Verilog.
- Skilled at designing LabVIEW based systems for data acquisition and control.
- Setup and Administration of Linux and Windows based servers & IoT devices for secure local and remote access.
- MS, Electrical & Computer Engineering May’09
University of Utah, Salt Lake City
- BE, Electronics & Communication Engineering Jun’07
Osmania University, Hyderabad, India
- N. Chappanda, A. Mathur and M. Tabib-Azar, “A study of surface diffusion of metals in tungsten for NEMS applications,” 2011 16th International Solid-State Sensors, Actuators and Microsystems Conference, Beijing, 2011, pp. 1364-1367.doi: 10.1109/TRANSDUCERS.2011.5969523
- Abhishek Mathur, Arun Jayachandran, Ramya Venumbaka “Low Leakage SRAM design using sleep transistor stack”
Relevant Work Experience
- Design Electronics Engineer & Flow Simulations Engineer, KAM Controls Inc Feb’2011-Present
- Project management of measurement and analysis system design in Hazardous areas for ATEX, IECEx, CSA certified instruments.
- Design and Layout of Printed Circuit boards for the electronics of optical, RF and microwave instrument sensors.
- Build, assemble and test prototypes of online measurement instruments in specified flow conditions.
- Guiding and training production teams.
- Writing firmware and PC based programs to interface and monitor instruments.
- Conducting fluid simulations using Conformal Design Flow software.
- Recommending flow conditioning solutions based on results of CFD simulation and installation conditions.
- Network security and server setup administration with support for local and remote users
- MEMS Research, University of Utah Post Graduate Researcher, May’09 – Dec’10
- Successfully designed and built a unique modular Atomic Layer Deposition system and programmed its mass flow controllers and temperature controllers in Labview.
- Invited to present at the NanoUtah 2010 conference.
- Created current custom drivers in Labview for data acquisition, sensor calibration and control for laboratory equipment.
- Designed and successfully built very sensitive electric-field sensors and circuitry using a micro-to-nano geometrical adaptor and nano-scale JFETs which can be used to map biological signals (EEG and EKG) as well as detect hidden objects.
- Invited to present at the Nano Utah 2009 Conference
- Deposited few atomic layer Graphene film on a different substrates and tested prototypes of next generation NEMS based Electronics.
- Also invited to present at NanoUtah 2010 conference and presented at the IEEE Transducers 2011 conference
- MIC Electronics Ltd, Hyderabad, India Hardware Design Engineer Intern, Oct’06- Mar’07
- Involved in the design, fabrication and programming of microcontroller based GSM enabled equipment for remote programming of LED, LCD display boards. GPS coordinates of a mobile tag were tracked via SMS to a user desired location
- Skills: .Net Application Development using C#, Lab View, Verilog, C/C++, TCL, RTL & Gate Simulations, 8085/8086 Assembly Language, RS-232, MODBUS, I2C, SPI bus protocol, HART protocol over 4-20mA, USB, Bluetooth, Zigbee Designs, OpenVPN, Raspberry Pi programming, Star CCM+, AutoCAD, Inventor, Excel
- PCB Design Tools: Altium Designer , Cadence OrCAD, PADS PCB Design, Eagle
- Chip Design Tools: Cadence ICFB (Virtuoso Schematic, layout Editor, Spectre RF Analog Environment, Verilog XL, NC-Verilog, Mixed Mode Simulation, Abstract Generator, SOC Encounter) , Tanner EDA tools, Synopsys (PrimeTime, Design Compiler, TetraMAX) , Modelsim , Spice, NI Multisim, MATLAB, CAD Testing (Vis-2.0,OPUS,HITEC);
Relevant Course Work
- MS: Advanced Digital VLSI, Embedded Systems, Analog IC Testing, Digital VLSI Design, Analog IC Design, Asynchronous VLSI Design, VLSI Architecture, Digital Signal Processing, CAD for Digital Systems – Logic Synthesis and Optimization, Micro sensors and Actuators, Computer Architecture, Random Processes
- BE: Microprocessors, FPGA Design, C & Data Structures, C++ for Programmers, Digital & Analog Communications, Embedded Systems
Selected Academic Projects
- Low Power Cache Design using Sleep Transistors [Cadence ICFB, 0.13μmCMOS]
Designed and implemented an energy efficient Cache memory using low leakage SRAM cells. Power gating technique was implemented with sleep transistors using multi threshold library. The number of sleep transistors per cell was varied for analysis of the amount of leakage power in each case, using SPICE simulations.
- Vending Machine microcontroller design [Cadence ICFB, Synopsys DC, 0.5μmCMOS]
The design was implemented by using a finite state machine to acquire data from ROM and give the output to the dispensing mechanism as well as a VGA display based on a keypad input
- Third Order Elliptic Filter Based on Biquad Architecture Using Switched Capacitors [Cadence ICFB, 0.5μmCMOS]
The filter was designed to attain 3db cut-off at 50 KHz and a sampling frequency of 250 KHz. The design consisted of Op-Amp’s with a unity gain frequency of 16MHz used in conjunction with switched capacitor circuits to filter the input accurately.
The design was taped out; Chip was fabricated in a 0.5μm CMOS through MOSIS and successfully tested.
- Design of Standard Cell Library in 0.5μmCMOS Technology [Cadence ICFB, Synopsys DC, 0.5μmCMOS]
The Standard Cell Library consisting of basic gates with different inputs and drive strengths was designed in Cadence ICFB. This involved creating layout, cmos_sch and symbol, behavioral, extracted, analog extracted and abstract views, along with .lib, .lef, and .v information. This library is used to synthesize the MIPS controller state machine. The structural Verilog file is used for place and route using SOC Encounter. Clock tree synthesis is done and LVS is performed between extracted and schematic views.
- Microcontroller based GSM Mobile Phone [Embedded C, Assembly, RF,GPS]
Successfully implemented the project and presented a seminar on “Microcontroller Based GSM Mobile Phone”. The project involved the development of a micro controller based GSM mobile phone, delving into the domains of communication engineering, speech conversion, encryption, microcontroller interfacing and control, network sub systems and radio frequency management.
Selected Academic Projects
- 40+ hours per year of volunteering with local non profits and disaster relief like the Houston Food Bank, Project Cure, Books Between Kids and Exploration Green.
- Organised and volunteered for “ADSOPHOS”, a National Level Technical Symposium
- Won first prize in IEEE technical quiz Event held as part of IEEE STAC 2005
- Won first prize in Vendez-Le Event in IEEE SPAC 2006
- Participated in Paper presentation and Quiz events in IEEE STAC 2006 and volunteered for city wide publicity work